1. 27 Jul, 2021 19 commits
    • Peter Maydell's avatar
      v6.1.0-rc1
      f2da205c
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210727' into staging · 9ae1246a
      Peter Maydell authored
      
      target-arm queue:
       * hw/arm/smmuv3: Check 31st bit to see if CD is valid
       * qemu-options.hx: Fix formatting of -machine memory-backend option
       * hw: aspeed_gpio: Fix memory size
       * hw/arm/nseries: Display hexadecimal value with '0x' prefix
       * Add sve-default-vector-length cpu property
       * docs: Update path that mentions deprecated.rst
       * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
       * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
       * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
       * target/arm: Report M-profile alignment faults correctly to the guest
       * target/arm: Add missing 'return's after calling v7m_exception_taken()
       * target/arm: Enforce that M-profile SP low 2 bits are always zero
      
      # gpg: Signature made Tue 27 Jul 2021 11:46:17 BST
      # gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
      # gpg:                issuer "peter.maydell@linaro.org"
      # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
      # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
      # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
      # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE
      
      * remotes/pmaydell/tags/pull-target-arm-20210727:
        hw: aspeed_gpio: Fix memory size
        hw/arm/nseries: Display hexadecimal value with '0x' prefix
        target/arm: Add sve-default-vector-length cpu property
        target/arm: Export aarch64_sve_zcr_get_valid_len
        target/arm: Correctly bound length in sve_zcr_get_valid_len
        docs: Update path that mentions deprecated.rst
        hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
        hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
        hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
        target/arm: Report M-profile alignment faults correctly to the guest
        target/arm: Add missing 'return's after calling v7m_exception_taken()
        target/arm: Enforce that M-profile SP low 2 bits are always zero
        qemu-options.hx: Fix formatting of -machine memory-backend option
        hw/arm/smmuv3: Check 31st bit to see if CD is valid
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      9ae1246a
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into staging · 202abcd3
      Peter Maydell authored
      
      hw/nvme fixes
      
      * new PMR test (Gollu Appalanaidu)
      * pmr/sgl mapping fix (Padmakar Kalghatgi)
      * hotplug fixes (me)
      * mmio out-of-bound read fix (me)
      * big-endian host fixes (me)
      
      # gpg: Signature made Mon 26 Jul 2021 20:18:12 BST
      # gpg:                using RSA key 522833AA75E2DCE6A24766C04DE1AF316D4F0DE9
      # gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown]
      # gpg:                 aka "Klaus Jensen <k.jensen@samsung.com>" [unknown]
      # gpg: WARNING: This key is not certified with a trusted signature!
      # gpg:          There is no indication that the signature belongs to the owner.
      # Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468  4272 63D5 6FC5 E55D A838
      #      Subkey fingerprint: 5228 33AA 75E2 DCE6 A247  66C0 4DE1 AF31 6D4F 0DE9
      
      * remotes/nvme/tags/nvme-next-pull-request:
        tests/qtest/nvme-test: add mmio read test
        hw/nvme: fix mmio read
        hw/nvme: fix out-of-bounds reads
        hw/nvme: use symbolic names for registers
        hw/nvme: split pmrmsc register into upper and lower
        hw/nvme: fix controller hot unplugging
        tests/qtest/nvme-test: add persistent memory region test
        hw/nvme: error handling for too many mappings
        hw/nvme: unregister controller with subsystem at exit
        hw/nvme: mark nvme-subsys non-hotpluggable
        hw/nvme: remove NvmeCtrl parameter from ns setup/check functions
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      202abcd3
    • Joel Stanley's avatar
      hw: aspeed_gpio: Fix memory size · e229a179
      Joel Stanley authored
      The macro used to calculate the maximum memory size of the MMIO region
      had a mistake, causing all GPIO models to create a mapping of 0x9D8.
      The intent was to have it be 0x9D8 - 0x800.
      
      This extra size doesn't matter on ast2400 and ast2500, which have a 4KB
      region set aside for the GPIO controller.
      
      On the ast2600 the 3.3V and 1.8V GPIO controllers are 2KB apart, so the
      regions would overlap. Worse was the 1.8V controller would map over the
      top of the following peripheral, which happens to be the RTC.
      
      The mmio region used by each device is a maximum of 2KB, so avoid the
      calculations and hard code this as the maximum.
      
      Fixes: 36d737ee
      
       ("hw/gpio: Add in AST2600 specific implementation")
      Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
      Reviewed-by: default avatarRashmica Gupta <rashmica.g@gmail.com>
      Reviewed-by: default avatarCédric Le Goater <clg@kaod.org>
      Message-id: 20210713065854.134634-2-joel@jms.id.au
      [PMM: fix autocorrect error in commit message]
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      e229a179
    • Philippe Mathieu-Daudé's avatar
      hw/arm/nseries: Display hexadecimal value with '0x' prefix · b1c2a6bd
      Philippe Mathieu-Daudé authored
      
      Signed-off-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20210726150953.1218690-1-f4bug@amsat.org
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      b1c2a6bd
    • Richard Henderson's avatar
      target/arm: Add sve-default-vector-length cpu property · b3d52804
      Richard Henderson authored
      Mirror the behavour of /proc/sys/abi/sve_default_vector_length
      under the real linux kernel.  We have no way of passing along
      a real default across exec like the kernel can, but this is a
      decent way of adjusting the startup vector length of a process.
      
      Resolves: https://gitlab.com/qemu-project/qemu/-/issues/482
      
      
      Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Message-id: 20210723203344.968563-4-richard.henderson@linaro.org
      [PMM: tweaked docs formatting, document -1 special-case,
       added fixup patch from RTH mentioning QEMU's maximum veclen.]
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      b3d52804
    • Richard Henderson's avatar
      target/arm: Export aarch64_sve_zcr_get_valid_len · ce440581
      Richard Henderson authored
      
      Rename from sve_zcr_get_valid_len and make accessible
      from outside of helper.c.
      
      Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Message-id: 20210723203344.968563-3-richard.henderson@linaro.org
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      ce440581
    • Richard Henderson's avatar
      target/arm: Correctly bound length in sve_zcr_get_valid_len · dc0bc8e7
      Richard Henderson authored
      
      Currently, our only caller is sve_zcr_len_for_el, which has
      already masked the length extracted from ZCR_ELx, so the
      masking done here is a nop.  But we will shortly have uses
      from other locations, where the length will be unmasked.
      
      Saturate the length to ARM_MAX_VQ instead of truncating to
      the low 4 bits.
      
      Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Message-id: 20210723203344.968563-2-richard.henderson@linaro.org
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      dc0bc8e7
    • Mao Zhongyi's avatar
      docs: Update path that mentions deprecated.rst · a476b216
      Mao Zhongyi authored
      Missed in commit f3478392
      
       "docs: Move deprecation, build
      and license info out of system/"
      
      Signed-off-by: default avatarMao Zhongyi <maozhongyi@cmss.chinamobile.com>
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Message-id: 20210723065828.1336760-1-maozhongyi@cmss.chinamobile.com
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      a476b216
    • Peter Maydell's avatar
      hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS · 845d27a9
      Peter Maydell authored
      
      In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if
      the register is accessed NonSecure and the highest priority pending
      enabled exception (that would be returned in the VECTPENDING field)
      targets Secure, then the VECTPENDING field must read 1 rather than
      the exception number of the pending exception. Implement this.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20210723162146.5167-7-peter.maydell@linaro.org
      845d27a9
    • Peter Maydell's avatar
      hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING · 7caad657
      Peter Maydell authored
      
      The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of
      the register.  We were incorrectly masking it to 8 bits, so it would
      report the wrong value if the pending exception was greater than 256.
      Fix the bug.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20210723162146.5167-6-peter.maydell@linaro.org
      7caad657
    • Peter Maydell's avatar
      hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts · 41487794
      Peter Maydell authored
      
      The ISCR.ISRPENDING bit is set when an external interrupt is pending.
      This is true whether that external interrupt is enabled or not.
      This means that we can't use 's->vectpending == 0' as a shortcut to
      "ISRPENDING is zero", because s->vectpending indicates only the
      highest priority pending enabled interrupt.
      
      Remove the incorrect optimization so that if there is no pending
      enabled interrupt we fall through to scanning through the whole
      interrupt array.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20210723162146.5167-5-peter.maydell@linaro.org
      41487794
    • Peter Maydell's avatar
      target/arm: Report M-profile alignment faults correctly to the guest · d4f68839
      Peter Maydell authored
      
      For M-profile, we weren't reporting alignment faults triggered by the
      generic TCG code correctly to the guest.  These get passed into
      arm_v7m_cpu_do_interrupt() as an EXCP_DATA_ABORT with an A-profile
      style exception.fsr value of 1.  We didn't check for this, and so
      they fell through into the default of "assume this is an MPU fault"
      and were reported to the guest as a data access violation MPU fault.
      
      Report these alignment faults as UsageFaults which set the UNALIGNED
      bit in the UFSR.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20210723162146.5167-4-peter.maydell@linaro.org
      d4f68839
    • Peter Maydell's avatar
      target/arm: Add missing 'return's after calling v7m_exception_taken() · 0c317eb3
      Peter Maydell authored
      
      In do_v7m_exception_exit(), we perform various checks as part of
      performing the exception return.  If one of these checks fails, the
      architecture requires that we take an appropriate exception on the
      existing stackframe.  We implement this by calling
      v7m_exception_taken() to set up to take the new exception, and then
      immediately returning from do_v7m_exception_exit() without proceeding
      any further with the unstack-and-exception-return process.
      
      In a couple of checks that are new in v8.1M, we forgot the "return"
      statement, with the effect that if bad code in the guest tripped over
      these checks we would set up to take a UsageFault exception but then
      blunder on trying to also unstack and return from the original
      exception, with the probable result that the guest would crash.
      
      Add the missing return statements.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20210723162146.5167-3-peter.maydell@linaro.org
      0c317eb3
    • Peter Maydell's avatar
      target/arm: Enforce that M-profile SP low 2 bits are always zero · 888f470f
      Peter Maydell authored
      
      For M-profile, unlike A-profile, the low 2 bits of SP are defined to be
      RES0H, which is to say that they must be hardwired to zero so that
      guest attempts to write non-zero values to them are ignored.
      
      Implement this behaviour by masking out the low bits:
       * for writes to r13 by the gdbstub
       * for writes to any of the various flavours of SP via MSR
       * for writes to r13 via store_reg() in generated code
      
      Note that all the direct uses of cpu_R[] in translate.c are in places
      where the register is definitely not r13 (usually because that has
      been checked for as an UNDEFINED or UNPREDICTABLE case and handled as
      UNDEF).
      
      All the other writes to regs[13] in C code are either:
       * A-profile only code
       * writes of values we can guarantee to be aligned, such as
         - writes of previous-SP-value plus or minus a 4-aligned constant
         - writes of the value in an SP limit register (which we already
           enforce to be aligned)
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
      Message-id: 20210723162146.5167-2-peter.maydell@linaro.org
      888f470f
    • Peter Maydell's avatar
      qemu-options.hx: Fix formatting of -machine memory-backend option · 95355829
      Peter Maydell authored
      
      The documentation of the -machine memory-backend has some minor
      formatting errors:
       * Misindentation of the initial line meant that the whole option
         section is incorrectly indented in the HTML output compared to
         the other -machine options
       * The examples weren't indented, which meant that they were formatted
         as plain run-on text including outputting the "::" as text.
       * The a) b) list has no rst-format markup so it is rendered as
         a single run-on paragraph
      
      Fix the formatting.
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Reviewed-by: default avatarIgor Mammedov <imammedo@redhat.com>
      Message-id: 20210719105257.3599-1-peter.maydell@linaro.org
      95355829
    • Joe Komlodi's avatar
      hw/arm/smmuv3: Check 31st bit to see if CD is valid · 1b41847a
      Joe Komlodi authored
      
      The bit to see if a CD is valid is the last bit of the first word of the CD.
      
      Signed-off-by: default avatarJoe Komlodi <joe.komlodi@xilinx.com>
      Message-id: 1626728232-134665-2-git-send-email-joe.komlodi@xilinx.com
      Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      1b41847a
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-migration-20210726a' into staging · ca4b5ef3
      Peter Maydell authored
      
      Migration fixes 2021-07-26
      
      Peter's fix for a bunch of races
       -> Seem to fix the occasional crash seen by Peter
      
      Wei's fix for migration with free page hinting
       -> Bug has been around for a while, but makes a huge difference
      
      My fix for OpenBSD test corner case
      
      Signed-off-by: default avatarDr. David Alan Gilbert <dgilbert@redhat.com>
      
      # gpg: Signature made Mon 26 Jul 2021 13:42:16 BST
      # gpg:                using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7
      # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full]
      # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A  9FA9 0516 331E BC5B FDE7
      
      * remotes/dgilbert-gitlab/tags/pull-migration-20210726a:
        migration: clear the memory region dirty bitmap when skipping free pages
        migration: Move the yank unregister of channel_close out
        migration: Teach QEMUFile to be QIOChannel-aware
        migration: Introduce migration_ioc_[un]register_yank()
        migration: Make from_dst_file accesses thread-safe
        migration: Fix missing join() of rp_thread
        tests/qtest/migration-test.c: use 127.0.0.1 instead of 0
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      ca4b5ef3
    • Peter Maydell's avatar
      Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' into staging · c08ccd1b
      Peter Maydell authored
      Fix icount accounting.
      Replace bitrev8 with revbit8.
      Fixes for set but not used warnings.
      
      # gpg: Signature made Mon 26 Jul 2021 22:45:37 BST
      # gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
      # gpg:                issuer "richard.henderson@linaro.org"
      # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
      # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F
      
      * remotes/rth-gitlab/tags/pull-tcg-20210726:
        tests/unit: Remove unused variable from test_io
        linux-user/syscall: Remove unused variable from execve
        hw/pci-hist/pnv_phb4: Fix typo in pnv_phb4_ioda_write
        hw/ppc/spapr_events: Remove unused variable from check_exception
        hw/audio/adlib: Remove unused variable in adlib_callback
        net/checksum: Remove unused variable in net_checksum_add_iov
        util/selfmap: Discard mapping on error
        accel/tcg: Remove unused variable in cpu_exec
        nbd/server: Mark variable unused in nbd_negotiate_meta_queries
        bitops.h: revert db1ffc32
      
       ("qemu/bitops.h: add bitrev8 implementation")
        accel/tcg: Remove unnecessary check on icount_extra in cpu_loop_exec_tb()
        accel/tcg: Don't use CF_COUNT_MASK as the max value of icount_decr.u16.low
      
      Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
      c08ccd1b
  2. 26 Jul, 2021 21 commits